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AS7C331MFT32A Scheda tecnica(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C331MFT32A Scheda tecnica(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 19 page  December 2004 Copyright © Alliance Semiconductor. All rights reserved. ® 12/23/04, v 1.3 Alliance Semiconductor 1 of 19 3.3V 1M × 32/36 Flow-through synchronous SRAM AS7C331MFT32A AS7C331MFT36A Features • Organization: 1,048,576 words × 32 or 36 bits • Fast clock to data access: 7.5/8.5/10 ns •Fast OE access time: 3.5/4.0 ns • Fully synchronous flow-through operation • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs Logic block diagram Selection guide -75 -85 -10 Units Minimum cycle time 8.5 10 12 ns Maximum clock access time 7.5 8.5 10 ns Maximum operating current 325 300 275 mA Maximum standby current 140 130 130 mA Maximum CMOS standby current (DC) 90 90 90 mA A[19:0] 20 18 20 20 Q0 Q1 1M × 32/36 Memory array Burst logic CLK CLR CE Address DQ CE CLK DQd CLK DQ Byte write registers register DQc CLK DQ Byte write registers DQb CLK DQ Byte write registers DQa CLK DQ Byte write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down DQ[a:d] 4 32/36 GWE BWE BWd ADV ADSC ADSP CLK CE0 CE1 CE2 BWc BWb BWa OE ZZ LBO OE CLK CLK 32/36 32/36 2 2 |
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