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ATTINY817-MFR. Scheda tecnica(PDF) 85 Page - Microchip Technology |
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ATTINY817-MFR. Scheda tecnica(HTML) 85 Page - Microchip Technology |
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85 / 492 page ![]() 13.3.2.3 Interrupt Response Time The minimum interrupt response time for all enabled interrupts is three CPU clock cycles: one cycle to finish the ongoing instruction, and two cycles to store the program counter to the stack. After the program counter is pushed on the stack, the program vector for the interrupt is executed. See also figure below, first diagram. The jump to the interrupt handler takes three clock cycles. If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. See also figure below, second diagram. ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 85 |
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