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ADC32RF83 Scheda tecnica(PDF) 114 Page - Texas Instruments

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Il numero della parte ADC32RF83
Spiegazioni elettronici  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADC32RF83 Scheda tecnica(HTML) 114 Page - Texas Instruments

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
Figure 237. Register 01Dh
7
6
5
4
3
2
1
0
DWELLIIR[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 238. Register 01Eh
7
6
5
4
3
2
1
0
DWELLIIR[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 107. Register 01Dh-01Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DWELLIIR
R/W
0h
DWELL time counter for the IIR output comparators. When the
IIR filter output crosses the upper thresholds FIL0THH or
FIL1THH, the IIR peak detector output flags are set. In order to
be reset, the output of the IIR filter must remain continuously
lower than the lower threshold (FIL0THL or FIL1THL) for the
period specified by the DWELLIIR value. This threshold is 16
bits and is specified in terms of fS / 8 clock cycles.
Example: if fS = 3 GSPS, fS / 8 = 375 MHz, and DWELLIIR =
0100h, then the DWELL time = 29 / 375 MHz = 1.36 µs.
8.5.13.11 Register 020h (address = 020h), Power Detector Page
Figure 239. Register 020h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RMSDET EN
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 108. Register 020h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0
RMSDET EN
R/W
0h
This bit enables the RMS power detector.
0 = Power detector disabled
1 = Power detector enabled



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