AM7953X-2JC datasheet(11/20 Pages) AMD

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SLIC Products

SWITCHING WAVEFORMS

Am79534/Am79535

Notes:

1. Unless otherwise noted, test conditions are BAT = –48 V, VCC =+5 V, VEE = –5V, RL = 600 Ω, CHP =0.22 µF,

RDC1 =RDC2 = 31.25 kΩ, CDC =0.1 µF, RD =51.1 kΩ, no fuse resistors, two-wire AC output impedance, programming

impedance (ZT) = 600 kΩ resistive, receive input summing impedance (ZRX)=300kΩ resistive. (See Table 2 for component

formulas.)

2. Overload level is defined when THD = 1%.

3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance

matches the impedance programmed by ZT.

4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.

5. These tests are performed with a longitudinal impedance of 90

Ω and metallic impedance of 300 Ω for frequencies below

12 kHz and 135

Ω for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.

6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.

7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system

design. The Anti-sat 2 region occurs at high loop resistances when |VBAT| – |VAX – VBX| is less than approximately 11 V.

8. “Midpoint” is defined as the connection point between two 300

Ω series resistors connected between A(TIP) and B(RING).

9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.

10. Assumes the following ZT network:

DET

tgkde

DET

tshdd

Note:

All delays measured at 1.4 V level.

E1 to DET

E0 to DET

tshde

tgkde

tshde

tshd0

tgkdd

tgkd0

16854C-02

VTX

RSN

300 k

Ω

300 k

Ω

30 pF

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