ASM3I623S00AG-08-ST datasheet(2/16 Pages) ALSC

2 / 16 page

July 2005

ASM3P623S00A/B/C/D/E/F

rev 1.0

Zero Cycle Slip Peak EMI Reduction IC

2 of 16

Notice: The information in this document is subject to change without notice.

Spread Spectrum Frequency Generation

The clocks in digital systems are typically square waves

with a 50% duty cycle and as frequencies increase the

edge rates also get faster. Analysis shows that a square

wave is composed of fundamental frequency and

harmonics. The fundamental frequency and harmonics

generate the energy peaks that become the source of

EMI. Regulatory agencies test electronic equipment by

measuring the amount of peak energy radiated from the

equipment. In fact, the peak level allowed decreases as

the frequency increases. The standard methods of

reducing EMI are to use shielding, filtering, multi-layer

PCBs etc. These methods are expensive. Spread

spectrum clocking reduces the peak energy by reducing

the Q factor of the clock. This is done by slowly

modulating the clock frequency. The ASM3P623S00X

uses the center modulation spread spectrum technique in

which the modulated output frequency varies above and

below the reference frequency

with

a specified

modulation rate. With center modulation, the average

frequency is the same as the unmodulated frequency and

there is no performance degradation

Cycle Slip

Cycle slip occurs when the output clock edge

‘wanders’ away from the corresponding input clock

edge. There are two types of cycle slips – a Differential

cycle slip and an Integral cycle slip. The differential

cycle slip is caused due the clock edge variation over

one modulation cycle. It is defined by the maximum

amount of ‘wander’ the clock edge will have within one

modulation cycle. Integral cycle slip occurs due to the

accumulation of the cycle slip over successive modulation

cycles. In ASM3P623S00A/B/C/D/E/F the differential cycle

slip is within the value mentioned in the

“Differential Cycle

Slip and Spread Spectrum Control Table” and the Integral

Cycle Slip is ‘Zero’.

Pin Configuration

CLKIN

CLKOUT1

VDD

CLKOUT6

CLKOUT7

CLKOUT4

CLKOUT5

VDD

GND

CLKOUT8

GND

SS%

ASM3P623S00 D/E/F

CLKOUT2

CLKOUT3

SSON

DLY CNTRL

CLKIN

SS%

VDD

SSON

CLKOUT

GND

ASM3P623S00A/B/C

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