ASM3I623S00AG-08-SR datasheet(1/16 Pages) ALSC

Il numero della parte	ASM3I623S00AG-08-SR

Spiegazioni elettronici	Zero Cycle Slip Peak EMI reduction IC

PDF	16 Pages

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Produttore elettronici	ALSC [Alliance Semiconductor Corporation]

Homepage	https://www.alliancememory.com

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1 / 16 page

July 2005

ASM3P623S00A/B/C/D/E/F

rev 1.0

Alliance Semiconductor

2575 Augustine Drive

• Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

Zero Cycle Slip Peak EMI reduction IC

General Features

Input frequency range: 20MHz - 50MHz.

Zero input - output propagation delay.

Low-skew outputs.

Output-output skew less than 250pS.

Device-device skew less than 700pS.

Less than 200pS cycle-to-cycle jitter is compatible

with Pentium

® based systems.

Available in 16pin, 150mil SOIC, 4.4mm TSSOP

(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,

4.4mm TSSOP Packages (ASM3P623S00A/B/C).

3.3V operation

Advanced 0.35µ CMOS technology.

The First True Drop-in Solution.

Functional Description

ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed clocks. It accepts one

reference input and drives out eight low-skew clocks. It is

available in a 16pin package. The ASM3P623S00A/B/C is

the eight-pin version of the ASM3P623S00. It accepts one

reference input and drives out one low-skew clock.

All parts have on-chip PLLs that lock to an input clock on

the CLKIN pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad, internal to the device.

Multiple ASM3P623S00D/E/F devices can accept the same

input clock and distribute it. In this case, the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than 250pS, and the output-to-output skew is

guaranteed to be less than 250pS.

Please refer

“Differential Cycle Slips and Spread Spectrum

Control Table” for deviations and differential Cycle Slips

for ASM3P623S00A/B/C and the ASM3P623S00D/E/F

devices

The ASM3P623S00A/B/C and the ASM3P623S00D/E/F

are available in two different configurations, as shown in

the ordering information table.

Block Diagram

VSS

CLKIN

Reference

Divider

Feedback

Divider

Modulation

Phase

Detector

Loop

Filter

VCO

Feedforward

Divider

PLL

VDD

CLKOUT

SSON

SS%

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