EM78F734N datasheet(3/100 Pages) EMC

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Contents

Product Specification (V1.4) 09.05.2019

 iii

Contents

General Description ··············································································1

Features ······························································································1

Pin Assignment ····················································································3

Pin Description·····················································································5

Block Diagram······················································································7

Functional Description ··········································································8

6.1 Operational Registers .......................................................................................8

6.1.1

R0 (Indirect Addressing Register) .......................................................................8

6.1.2

R1 (Timer Clock/Counter) ...................................................................................8

6.1.3

R2 (Program Counter) and Stack........................................................................8

6.1.4

R3 (Status Register)..........................................................................................11

6.1.5

R4 (RAM Select Register) .................................................................................11

6.1.6

Bank 0 R5 ~ R8 (Port 5 ~ Port 8) ......................................................................11

6.1.7

Bank 0 R9 TBPTL (Low byte of Table Pointer Register) ...................................11

6.1.8

Bank 0 RA (Wake- up Control Register) ...........................................................12

6.1.9

Bank 0 RB (EEPROM Control Register) ...........................................................12

6.1.10 Bank 0 RC (EEPROM Address)........................................................................13

6.1.11 Bank 0 RD (EEPROM Data) .............................................................................13

6.1.12 Bank 0 RE (CPU Operating Control Register) ..................................................13

6.1.13 Bank 0 RF (Interrupt Status Register)...............................................................14

6.1.14 R10 ~ R3F .........................................................................................................15

6.1.15 Bank 1 R5 TC1CR (Timer 1 Control) ................................................................15

6.1.16 Bank 1 R6 TC1DA (Timer 1 Data Buffer A) .......................................................18

6.1.17 Bank 1 R7 TC1DB (Timer 1 Data Buffer B).......................................................18

6.1.18 Bank 1 R8 OSCR (Oscillator Control) ...............................................................18

6.1.19 Bank 1 R9 TC2DA (Timer 2 Data Buffer A) .......................................................19

6.1.20 Bank 1 RA TC2DB (Timer 2 Data Buffer B) ......................................................19

6.1.21 Bank 1 RB ~RE .................................................................................................19

6.1.22 Bank 1 RF (Interrupt Status Register)...............................................................19

6.1.23 Bank 2 R5 AISR (ADC Input Select Register)...................................................20

6.1.24 Bank 2 R6 ADCON (A/D Control Register) .......................................................21

6.1.25 Bank 2 R7 ADOC (A/D Offset Calibration Register) .........................................22

6.1.26 Bank 2 R8 ADDH (AD High 8-Bit Data Buffer) ..................................................22

6.1.27 Bank 2 R9 ADDL (AD Low 4-Bit Data Buffer) ...................................................22

6.1.28 Bank 2 RA ~ RE ................................................................................................23

6.1.29 Bank 2 RF (Pull-high Control Register 1)..........................................................23

6.1.30 Bank 3 R5..........................................................................................................23

6.1.31 Bank 3 R6 TBPTH (High Byte of Table Pointer Register) .................................23

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