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DF69 Scheda tecnica(PDF) 8 Page - PADAUK Technology. |
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DF69 Scheda tecnica(HTML) 8 Page - PADAUK Technology. |
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8 / 106 page ![]() DF69 DC Fan Controller 1. Features 1-1. High Performance RISC CPU Array Patented Field Programmable Processor Array (FPPA™) Technology Operating modes: 8 processing units FPPA TM mode 4Kx16 bits OTP user program memory for 8 FPP units 208 Bytes data RAM for all FPP units 106 powerful instructions All instructions are 1T except indirect memory access, including branch instructions Programmable stack pointer to provide adjustable stack level Direct and indirect addressing modes for data and instructions All data memories are available for use as an index pointer Support security function to protect OTP data Separated IO and memory space to reduce firmware overhead in space exchange 1-2. System Functions Clock sources : internal high RC oscillator (IHRC), internal low RC oscillator (ILRC) and crystal oscillator Internal High RC Oscillator (IHRC) frequency Band-gap circuit to provide 1.20V reference voltage One hardware 16-bit timer One hardware 8-bit timer Up to 11-channel 10-bit resolution ADC with 1-channel for internal band-gap reference voltage One 10-bit hardware PWM generator PWM protection mechanism One 1T hardware multiplier One Hall comparator One general purpose comparator 16 IO pins with 10 mA capability and optional pull-high resistor Three levels of VDD voltage detection: 4.0V, 3.0V, 2.0V. Eight levels of LVD reset ~ 4.1V, 3.6V, 3.1V, 2.8V, 2.5V, 2.2V, 2.0V, 1.8V Selectable four external interrupt pins: PA0 or PA7, PB0 or PB7 Support fast wake-up Every IO pin can be configured to enable wake-up function Operating voltage range: 2.2V ~ 5.5V Operating temperature range: -40°C ~ 85°C for normal condition, -40°C ~ 105°C for special condition* Operating frequency range: DC ~ 8MHz@VDD≧3.3V; DC ~ 4MHz@VDD≧2.5V; DC ~ 2MHz@VDD≧2.2V Low power consumption Ioperating ~ 1.7mA@1MIPS, VDD=5.0V; Ioperating ~ 10uA@ ILRC~12KHz, VDD=3.3V Ipower down ~ 1uA@VDD=5.0V; Ipower down~ 0.5uA@VDD=3.3V 10-pin MSOP10 package *Please see the item 4.1 for special condition. ©Copyright 2018, PADAUK Technology Co. Ltd Page 8 of 106 PDK-DS-DF69_V003 – Apr. 18, 2018 |
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