MX25L3233FM1I-08G datasheet(9/84 Pages) MCNIX

9 / 84 page

MX25L3233F

P/N: PM2113

Rev. 1.6, March 10, 2017

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or pro-

gramming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command se-

quences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC

power-up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and complet-

ed on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic

Signature command (RES).

I. Block lock protection

- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be

protected as read only. The protected area definition is shown as table of "Table 1. Protected Area Sizes", the

protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits.

- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0, TB) bits and

SRWD bit.

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