IN74ACT112D datasheet(4/5 Pages) INTEGRAL

Il numero della parte	IN74ACT112D

Spiegazioni elettronici	DUAL J-K FLIP-FLOP WITH SET AND RESET

PDF	5 Pages

Scroll/Zoom	100%

Produttore elettronici	INTEGRAL [Integral Corp.]

Homepage	http://www.iksemi.com/

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4 / 5 page

IN74ACT112

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

°C

-40

°C to

°C

Unit

Min

Max

Min

Max

fmax

Maximum Clock Frequency (Figure 1)

145

125

MHz

tPLH

Propagation Delay, Clock to

Q or Q

(Figure 1)

1.0

14.0

1.0

15.0

tPHL

Propagation Delay, Clock to

Q or Q

(Figure 1)

1.0

14.0

1.0

14.5

tPLH

Propagation Delay, Set or Reset to

Q or

(Figure 2)

1.0

12.0

1.0

12.5

tPHL

Propagation Delay, Set or Reset to

Q or

(Figure 2)

1.0

12.5

1.0

13.0

CIN

Maximum Input Capacitance

4.5

Typical @25

°C,VCC=5.0

CPD

Power Dissipation Capacitance

TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

°C

-40

°C to

°C

Unit

tsu

Minimum Setup Time, J or K to Clock

(Figure 3)

2.0

2.5

Minimum Hold Time, Clock to J or K

(Figure 3)

2.0

Minimum Pulse Width, Clock (Figure 1)

5.0

6.0

Minimum Pulse Width,Set or Reset (Figure

5.5

6.0

trec

Minimum Recovery Time, Set or Reset to

Clock (Figure 2)

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