VT6307L datasheet(34/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

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Offset 90 (Set), 94 (Clear) – Iso Xmit Interrupt Events RW

31-8 Reserved

........................................ always reads 0

7-0

Isochronous Transmit Context . default = undefined

An interrupt is generated by an isochronous transmit

context

“Output

Last

DMA”

command

completes and its “i” bits are set to “interrupt always”.

Software clears the bits in this register by writing one

bits to the “Clear” address. Bits in this register will

only get set to one if the corresponding bits in the

mask register are set to one.

Offset 98 (Set), 9C (Clear) – Iso Xmit Interrupt Mask . RW

31-8 Reserved

........................................ always reads 0

7-0

Iso Transmit Context Mask....... default = undefined

Setting bits in this register enables interrupts to be

generated by the corresponding isochronous transmit

context

Offset A0 (Set), A4 (Clear) – Iso Rcv Interrupt Events RW

31-4 Reserved

........................................ always reads 0

3-0

Isochronous Receive Context ... default = undefined

An interrupt is generated by an isochronous receive

context if an “Input Last DMA” command completes

and its “i” bits are set to “interrupt always”. Software

clears the bits in this register by writing one bits to

the “Clear” address. Bits in this register will only get

set to one if the corresponding bits in the mask

Offset A8 (Set), AC (Clear) – Iso Rcv Interrupt Mask.. RW

31-4 Reserved

........................................ always reads 0

3-0

Iso Receive Context Mask.......... default = undefined

Setting bits in this register enables interrupts to be

generated by the corresponding isochronous receive

context

Offset B3-B0 – Initial Bandwidth Available ................... RW

31-13 Reserved

........................................always reads 0

12-0 Initial Bandwidth Available.............default = 1333h

Offset B7-B4 – Initial Channels Available High............. RW

31-0 Initial Channels Available..... default = FFFF FFFFh

Offset BB-B8 – Initial Channels Available Low............. RW

31-0 Initial Channels Available..... default = FFFF FFFFh

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