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Motore di ricerca datesheet componenti elettronici |
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AM29N323D Scheda tecnica(PDF) 13 Page - Advanced Micro Devices |
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AM29N323D Scheda tecnica(HTML) 13 Page - Advanced Micro Devices |
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13 / 48 page  12 Am29N323D August 8, 2002 ■ When WP# is at VIL, the two outermost sectors are locked. ■ When VPP is at VIL, all sectors are locked. The following hardware data protection measures pre- vent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. |
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