BLUENRG-355VC datasheet(6/72 Pages) STMICROELECTRONICS

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Figure 2. Bus matrix

1.2

ARM Cortex–M0+ core with MPU

The BlueNRG-LP contains an ARM Cortex-M0+ microcontroller core. The Cortex-M0+ was developed to provide

a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-power

consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Cortex-M0+ can run from 1 MHz up to 64 MHz.

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage

pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but

powerful instruction set and extensively optimized design, providing high-end processing hardware including a

single-cycle multiplier.

The interrupts are handled by the Cortex-M0+ Nested Vector Interrupt Controller (NVIC). The NVIC controls

specific Cortex-M0+ interrupts as well as the BlueNRG-LP peripheral interrupts. With its embedded ARM core, the

BlueNRG-LP family is compatible with all ARM tools and software.

1.3

Memories

1.3.1

Embedded Flash memory

The Flash controller implements the erase and program Flash memory operation. The flash controller also

implements the read and write protection.

The Flash memory features are:

•

Memory organization:

–

1 bank of 256 kB

–

Page size: 2 kB

–

Page number 128

•

32-bit wide data read/write

BlueNRG-LP

ARM Cortex–M0+ core with MPU

DS13282 - Rev 2

page 6/72

BLUENRG-355VC Scheda tecnica(PDF) 6 Page - STMicroelectronics