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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STM32H747AI Scheda tecnica(PDF) 25 Page - STMicroelectronics |
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STM32H747AI Scheda tecnica(HTML) 25 Page - STMicroelectronics |
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25 / 252 page  DS12930 Rev 1 15/242 STM32H747xI/G Functional overview 46 Figure 3. ART™ accelerator schematic and environment 3.4 Boot modes By default, the boot codes are executed simultaneously by both cores. However, by programming the appropriate Flash user option byte, it is possible to boot from one core while clock-gating the other core. At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: • All Flash address space • Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed by the Cortex®-M4 core) MSv39757V2 64-bit AXI bus matrix Flash bank 1 Flash bank 2 AXI SRAM QSPI FMC AHB from D2 domain 32-bit bus 64-bit bus Bus multiplexer Legend Master interface Slave interface AXI AHB ART accelerator AHB switch Non-cacheable access path Cacheable access path AXI access AHB access D1 domain Control control Cache memory 64 x 256-bit Cache memory 64 x 256-bit Cache buffer 1 x 256-bit Cache non- cacheable access Detect of write to cacheable page instruction fetch cache hit cache miss cache refill Cache manager |
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