XIO2000AI datasheet(59/165 Pages) TI

59 / 165 page

Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

Table 4−1. PCI Express Configuration Register Map (Continued)

OFFSET

GPIO data†

GPIO control†

0B4h

Reserved

0B8h−0BCh

Control and diagnotic register 0†

0C0h

Control and diagnotic register 1†

0C4h

Control and diagnotic register 2†

0C8h

Reserved

0CCh

Subsystem access†

0D0h

General control†

0D4h

Reserved

Clock run status†

Clock mask†

Clock control†

0D8h

Reserved

Arbiter time-out status

Arbiter request mask†

Arbiter control†

0DCh

Serial IRQ edge control†

Reserved

Serial IRQ mode control†

0E0h

Reserved

Serial IRQ status

0E4h

Reserved

0E8h−0FCh

† One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

4.1

Vendor ID Register

This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas Instruments.

PCI register offset:

00h

Read-only

Default value:

104Ch

BIT NUMBER

RESET STATE

4.2

Device ID Register

This 16-bit read-only register contains the value 8231h, which is the device ID assigned by TI for the bridge.

PCI register offset:

02h

Read-only

Default value:

8231h

BIT NUMBER

RESET STATE

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