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AT28C010 Scheda tecnica(PDF) 11 Page - Microchip Technology |
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AT28C010 Scheda tecnica(HTML) 11 Page - Microchip Technology |
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11 / 31 page ![]() Note: 1. CE may be delayed up to tACC‑tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE‑tOE after the falling edge of CE without impact on tCE or by tACC‑tOE after an address change without impact in tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 5. If CE is de-asserted, it must remain de-asserted for at least 50 ns during read operations, otherwise incorrect data may be read. 5.3 AC Read Waveforms High-Z High-Z t CE t OE t ACC t ACC t DF t OH t CE t OE t ACC t DF t OH 5.4 Input Test Waveforms and Measurement Level AC DRIVING LEVELS AC MEASUREMENT LEVELS 3.0V 0.0V 1.5V 5.5 Output Test Load 5.0V 1.8K 1.3K OUTPUT PIN 100 pF AT28C010 Device Operation © 2020 Microchip Technology Inc. DS20006311A-page 11 |
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