INA239 datasheet(18/44 Pages) TI

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default power-up register values are shown in the reset column for each register description. Links to the register

descriptions are shown in Section 7.6.

7.5 Programming

7.5.1 Serial Interface

The primary communication between the INA239 and the external MCU is through the SPI bus, which provides

full-duplex communications in a main-secondary configuration. The external MCU is always the primary or main

SPI device, sending command requests on the MOSI pin, and receiving device responses on the MISO pin. The

INA239 is always an SPI secondary device, receiving command requests and sending responses (status,

measured values) to the external MCU over the MISO pin.

• SPI is a 4-pin interface with pins as:

– CS - SPI Chip Select (input)

– SCLK - SPI Clock (input)

– MOSI - SPI Secondary In / Main Out data (input)

– MISO - SPI Secondary Out / Main In data (tri-state output)

• The SPI frame size is variable in length depending on the INA239 register accessed through the SPI interface

as following:

– Main to Secondary (MOSI): 6 bits for register Address; 1 bit low; 1 R/W bit (read / not write); variable

length of low bits depending on the INA239 register length.

– Secondary to Main (MISO): 8 bits low; variable length of bits depending on the INA239 register length.

• SPI bit-speed up to 10 Mbit/s

• Both Main commands and INA239 data are shifted MSB first, LSB last

• The data on the MOSI line is sampled on the falling edge of SCLK

• The data on the MISO line is shifted out on the rising edge of SCLK

The SPI communication starts with the CS falling edge, and ends with CS rising edge. The CS high level keeps

secondary SPI interface in an idle state, and MISO output is tri-stated.

Since the MISO output is push-pull it is ideal to have the INA239 supply at the same voltage as the primary

device I/O supply. If different supply voltages are used, level translation is recommended.

7.5.1.1 SPI Frame

SPI communication to the INA239 device is performed through register address access. Communication to every

that the current SPI frame will read from a device register while setting the R/W bit to "0" indicates the current

SPI frame will write data to a device register.

MISO

MOSI

ADDR

DATA

MSB

DATA

LSB

. . . .

. . . . . .

16 ± 24 bits

SCLK

Figure 7-7. SPI Read Frame

INA239

SLYS027 – JANUARY 2021

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