ADF4401ABCEZ datasheet(17/39 Pages) AD

17 / 39 page

Data Sheet

ADF4401A

Rev. 0 | Page 17 of 39

SPI Stream Mode

The ADF4401A supports stream mode, where data bits are

loaded to or read from registers serially without writing the

time critical applications when a large amount of data must be

transferred or when some registers must be updated repeatedly.

The slave device starts reading or writing data to this address

and continues as long as CS is asserted and single-byte writes

are not enabled (Bit 7 in the REG0001 register). The slave device

automatically increments or decrements the address depending

on the setting of the address ascension bit (Bit 2 in the REG0000

The instruction header starts with a Logic 0 to indicate a write

sequence and addresses the register. Then, the data for registers

(N, N − 1, and N − 2) are loaded consecutively without any

assertion in CS.

The registers are organized into eight bits, and if a register

requires more than eight bits, sequential register addresses are

used. This organization enables using stream mode and simplifies

loading. For example, FRAC1WORD is stored in the REG0017,

REG0016, REG0015, and REG0014 registers (MSB to LSB).

These registers can be loaded by using the REG0016 register

and sending the whole 24-bit data afterward, as shown in Figure 5.

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