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SN74LS228 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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SN74LS228 Scheda tecnica(HTML) 3 Page - Texas Instruments |
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3 / 10 page ![]() SN74LS228 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10–3 logic diagram (positive logic) 1 9 3 15 4 5 6 7 2 14 13 12 11 10 OE CLR LDCK UNCK D0 D1 D2 D3 IR OR Q0 Q1 Q2 Q3 16 16 16 16 Ring Counter CTR DIV 16 Write Address Ring Counter CTR DIV 16 Read Address COMP RAM 16 × 4 + CT = 1 + CT = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P Q 1A 2A C5 1 16 EN ≥1 1A,5D 2A 1 16 S 1D C1 S 2D C2 R 3D C3 R 4D C4 Q=P+1 P=Q+1 P=Q EMPTY |
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