LM4846TL datasheet(10/19 Pages) NSC

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Application Information (Continued)

SPI DESCRIPTION

0. I

2CSPI_SEL: This pin is tied HIGH for SPI mode.

1. The data bits are transmitted with the MSB first.

2. The maximum clock rate is 1MHz for the CLK pin.

3. CLK must remain HIGH for at least 500ns (t

CH ) after the

rising edge of CLK, and CLK must remain LOW for at least

500ns (t

CL) after the falling edge of CLK.

4. The serial data bits are sampled at the rising edge of CLK.

Any transition on DATA must occur at least 100ns (t

DS)

before the rising edge of CLK. Also, any transition on DATA

must occur at least 100ns (t

DH) after the rising edge of CLK

and stabilize before the next rising edge of CLK.

5.ID_ENB should be LOW only during serial data transmis-

sion.

6. ID_ENB must be LOW at least 100ns (t

ES ) before the first

rising edge of CLK, and ID_ENB has to remain LOW at least

100ns (t

EH) after the eighth rising edge of CLK.

7. If ID_ENB remains HIGH for more than 100ns before all 8

bits are transmitted then the data latch will be aborted.

8. If ID_ENB is LOW for more than 8 CLK pulses then only

the first 8 data bits will be latched and activated when

ID_ENB transitions to logic-high.

9. ID_ENB must remain HIGH for at least 100ns (t

EL ) to latch

in the data.

10. Coincidental rising or falling edges of CLK and ID_ENB

are not allowed. If CLK is to be held HIGH after the data

transmission, the falling edge of CLK must occur at least

100ns (t

CS) before ID_ENB transitions to LOW for the next

set of data.

201668F4

FIGURE 4. I

2C Timing Diagram

20166824

FIGURE 5. SPI Timing Diagram

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