ADPA7007AEHZ-R7 datasheet(16/23 Pages) AD

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ADPA7007

Data Sheet

Rev. 0 | Page 16 of 23

THEORY OF OPERATION

The simplified architecture of the ADPA7007 power amplifier

is shown in Figure 54. The ADPA7007 is a cascaded, three-

stage amplifier with a combined gain of 21.5 dB and a PSAT

value of 31.5 dBm.

The drain current is controlled by the voltage on the VGG1 and

VGG2 pins. These pins must be connected together and driven

by a negative voltage in the −1.5 V to 0 V range (typical gate

bias voltage for a quiescent drain current bias of 1400 mA is

−0.685 V). Simplified bias pin connections to the dedicated

gain stages are shown in Figure 54.

VDD5

VDD3

VDD1

VDD6

VGG1 VGG2

VDD4

VDD2

RFOUT

RFIN

Figure 54. Simplified Architecture of ADPA7007

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, the diode rectifies the RF power and makes the RF

power available for measurement as a dc voltage at VDET. To

allow temperature compensation of VDET, an identical and

symmetrically located circuit (minus the coupled RF power) is

available via VREF. The difference of VREF − VDET provides a

temperature compensated signal that is proportional to the RF

output.

To obtain optimal performance from the ADPA7007 and avoid

damaging the device, follow the recommended biasing

sequences described in the Applications Information section.

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