UD9926L-S08-R datasheet(2/7 Pages) VBSEMI

2 / 7 page

Notes:

a. Pulse test; pulse width

≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Static

Gate Threshold Voltage

VGS(th)

VDS = VGS, ID = 250 µA

0.6

1.5

Gate-Body Leakage

IGSS

VDS = 0 V, VGS = ± 12 V

± 100

Zero Gate Voltage Drain Current

IDSS

VDS = 20 V, VGS = 0 V

µA

VDS = 20 V, VGS = 0 V, TJ = 55 °C

On-State Drain Currenta

ID(on)

VDS ≥ 5 V, VGS = 4.5 V

Drain-Source On-State Resistancea

RDS(on)

VGS = 4.5 V, ID = 7.1 A

0.019

0.025

VGS = 2.5 V, ID = 6.0 A

0.026

0.035

Forward Transconductancea

gfs

VDS = 10 V, ID = 7.1 A

Diode Forward Voltagea

VSD

IS = 1.7 A, VGS = 0 V

1.2

Dynamicb

Total Gate Charge

VDS = 10 V, VGS = 4.5 V, ID = 7.1 A

9.5

Gate-Source Charge

Qgs

1.5

Gate-Drain Charge

Qgd

2.5

Gate Resistance

f = 1 MHz

1.6

2.7

Turn-On Delay Time

td(on)

VDD = 10 V, RL = 10 Ω

ID ≅ 1 A, VGEN = 4.5 V, Rg = 10 Ω

Rise Time

Turn-Off Delay Time

td(off)

Fall Time

Source-Drain Reverse Recovery Time

trr

IF = 1.7 A, dI/dt = 100 A/µs

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UD9926L-S08-R

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