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WM8569GEDS/V Scheda tecnica(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8569GEDS/V Scheda tecnica(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 36 page  Product Preview WM8569 w PP Rev 1.1 December 2005 19 ADCLRC ADCBCLK DOUT Input Word Length (IWL) 1/fs LEFT CHANNEL n 2 1 n-1 LSB MSB n 2 1 n-1 RIGHT CHANNEL NO VALID DATA 1 BCLK 1 BCLK Figure 15 DSP Mode A Timing Diagram – ADC Data Output DSP MODE B In DSP mode B, the MSB of DAC left channel data is sampled by the WM8569 on the first DACBCLK rising edge following a DACLRC rising edge. (Figure 16). Figure 16 DSP Mode B Timing Diagram – DAC Data Input The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 17). ADCLRC BCK DOUT Input Word Length (IWL) 1/fs LEFT CHANNEL n 2 1 n-1 LSB MSB n 2 1 n-1 RIGHT CHANNEL NO VALID DATA 1 Figure 17 DSP Mode B Timing Diagram – ADC Data Output |
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