SP5654SLASHKGSLASHMPAS datasheet(8/15 Pages) ZARLINK

Il numero della parte	SP5654/KG/MPAS

Spiegazioni elettronici	2.7GHz 3-WIRE BUS CONTROLLED SYNTHESISER

PDF	15 Pages

Scroll/Zoom	100%

Produttore elettronici	ZARLINK [Zarlink Semiconductor Inc]

Homepage	http://www.zarlink.com

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8 / 15 page

SP5654

Test Mode

Test Mode Description

Charge pump down 170

Charge pump up 170

Charge pump down 50

Charge pump up 50

FCOMP to P2; FPD/2 to P3;

Lock output switched to out of lock

condition

Lock output switched to inlock condition

These test modes are invoked by taking the clock input below VEE

d=don‘t care

Table 2 Test mode options

MODE

COMPATIBILITY

18 Bit Data entry

19 Bit Data entry

TD6380 plus

2 prescaler

TD6382 plus

4 prescaler

None

TD6381

TD6380

TD6382 plus

2 prescaler

None

TD6382

None

TD6381 plus

2 prescaler

Table 3. Programming compatibilities

FREQUENCY DATA

CLOCK

ENABLE

LSB

217

216

215

214

213

212

LSB

218

217

216

215

214

213

FREQUENCY DATA

=Enable set up time

=Data set up time

=Data hold time

=Clock–to–enable time

=Enable hold time

18–BIT

19–BIT

Fig. 4 Data format and timing

DATA ENTRY

MSB IS TRANSMITTED

FIRST

MSB

CLOCK

ENABLE

DATA

1.5V

CE tES

1.5V

=Clock low period

=Clock high period

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