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Block Read Programming Sequence

P

S

P

SCLK

SDATA

A

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

SMBus Hardware Interface

9

10

SDATA

SCLK

SMB Host

CDCE706

CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

1

7

1

1

8

1

1

7

1

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

8

1

8

1

1

Byte Count N

A

Data Byte 0

A

- - - - -

Data Byte N–1

A

P

Figure 5. Block Read Protocol

Figure 6. Timing Diagram Serial Control Interface

The following diagram shows how the CDCE706 clock synthesizer is connected to the SMBus. Note that the

Figure 7. SMBus Hardware Interface

11