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STM32H723VG Scheda tecnica(PDF) 144 Page - STMicroelectronics |
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STM32H723VG Scheda tecnica(HTML) 144 Page - STMicroelectronics |
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144 / 227 page ![]() Electrical characteristics STM32H723xE/G 144/227 DS13313 Rev 2 NAND controller waveforms and timings Figure 26 through Figure 29 represent synchronous waveforms, and Table 69 and Table 70 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration and a capacitive load (CL) of 30 pF: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 26. NAND controller waveforms for read access FMC_NWE FMC_NOE (NRE) FMC_D[15:0] tsu(D-NOE) th(NOE-D) MS32767V1 ALE (FMC_A17) CLE (FMC_A16) FMC_NCEx td(ALE-NOE) th(NOE-ALE) |
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