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STM32H723VG Scheda tecnica(PDF) 22 Page - STMicroelectronics |
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STM32H723VG Scheda tecnica(HTML) 22 Page - STMicroelectronics |
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22 / 227 page  Functional overview STM32H723xE/G 22/227 DS13313 Rev 2 Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: • 7 ECC bits are added per 32-bit word. • 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection. |
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