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TSB711AIYLT Scheda tecnica(PDF) 21 Page - STMicroelectronics

Il numero della parte TSB711AIYLT
Spiegazioni elettronici  Precision rail-to-rail input / output 36 V, 6 MHz op-amps
PDF  36 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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TSB711AIYLT Scheda tecnica(HTML) 21 Page - STMicroelectronics

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5.7
Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSB711, TSB711A, TSB712, TSB712A is 150 °C. The
junction temperature can be estimated as follows:
TJ=PD×Rtℎ−ja+TA
(10)
TJ is the die junction temperature
PD is the power dissipated in the package
Rth-ja is the junction to ambient thermal resistance of the package
TA is the ambient temperature
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:
PD= VCC×ICC + VCC+−VOUT ×ILoad
(11)
when the op-amp sources the current
PD= VCC×ICC + VOUT−VCC− ×ILoad
(12)
when the op-amp is sinks the current.
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.
5.8
Capacitive load and stability
Stability analysis must be performed for large capacitive loads over 100 pF. Increasing the load capacitance to
high values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting
a small resistor RISO (10 Ω to 30 Ω) in series with the output. This resistor significantly reduces ringing while
maintaining DC performance for purely capacitive loads. However, if there is a resistive load in parallel with the
capacitive load, a voltage divider is created introducing a gain error on the output and slightly reducing the output
swing. The error introduced is proportional to the ratio RISO / RL. RISO modifies the maximum capacitive load
acceptable from a stability point-of-view as described in the following figure:
Figure 45. Stability criteria with a serial resistor at different capacitive loads
Unstable
S
TSB711, TSB711A, TSB712, TSB712A, TSB714, TSB714A
Maximum power dissipation
DS12487 - Rev 6
page 21/36



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