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MCP39F511N Scheda tecnica(PDF) 6 Page - Microchip Technology |
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MCP39F511N Scheda tecnica(HTML) 6 Page - Microchip Technology |
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6 / 61 page ![]() 2015-2018 Microchip Technology Inc. DS20005473B-page 6 MCP39F511N 10-Bit SAR ADC Performance for Voltage Measurement Resolution NR —10 — bits Absolute Input Voltage VIN DGND -0.3 — DVDD +0.3 V Recommended Impedance of Analog Voltage Source RIN —— 2.5 k Integral Nonlinearity INL —±1 ±2 LSb Differential Nonlinearity DNL —±1 ±1.5 LSb Gain Error GERR —±1 ±3 LSb Offset Error EOFF —±1 ±2 LSb Clock and Timings UART Baud Rate UDB 1.2 — 115.2 kbps See Section 3.2 for protocol details Master Clock and Crystal Frequency fMCLK -2% 8 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC — 2 — % -40°C to +85°C only (Note 7) Internal Voltage Reference Internal Voltage Reference Tolerance VREF -2% 1.2 +2% V Temperature Coefficient TCVREF — 10 — ppm/°C TA = -40°C to +85°C, VREFEXT = 0 Output Impedance ZOUTVREF —2 — k Current, VREF AIDDVREF —40 — µA Voltage Reference Input Input Capacitance — — 10 pF Absolute Voltage on VREF+ Pin VREF+ AGND + 1.1V — AGND +1.3V V Power Specifications Operating Voltage AVDD, DVDD 2.7 — 3.6 V DVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR DGND —0.7 V TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. 2: Specification by design and characterization; not production tested. 3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. 4: Applies to Voltage Sag and Voltage Surge events only. 5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. 6: VIN =1 VPP =353 mVRMS @50/60 Hz. 7: Variation applies to internal clock and UART only. |
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