NAND01GR3B datasheet(36/64 Pages) STMICROELECTRONICS

36 / 64 page

Data protection

NAND01G-B, NAND02G-B

36/64

Data protection

The device has both hardware and software features to protect against program and erase

operations.

It features a Write Protect, WP, pin, which can be used to protect the device against program

and erase operations. It is recommended to keep WP at VIL during power-up and power-

down.

In addition, to protect the memory from any involuntary program/erase operations during

power-transitions, the device has an internal voltage detector which disables all functions

whenever VDD is below VLKO (see Table 22 and Table 23).

The device features a Block Lock mode, which is enabled by setting the Power-Up Read

Enable, Lock/Unlock Enable, PRL, signal to High.

The Block Lock mode has two levels of software protection.

●

Blocks Lock/Unlock

●

Blocks Lock-down

Refer to Figure 18 for an overview of the protection mechanism.

7.1

Blocks Lock

All the blocks are locked simultaneously by issuing a Blocks Lock command (see Table 10:

Commands).

All blocks are locked after power-up and when the Write Protect signal is Low.

Once all the blocks are locked, one sequence of consecutive blocks can be unlocked by

using the Blocks Unlock command.

Refer to Figure 23: Command Latch AC Waveforms for details on how to issue the

command.

7.2

Blocks Unlock

A sequence of consecutive locked blocks can be unlocked, to allow program or erase

operations, by issuing an Blocks Unlock command (see Table 10: Commands).

The Blocks Unlock command consists of four steps:

One bus cycle to setup the command

two or three bus cycles to give the Start Block Address (refer to Table 8, Table 9 and

Figure 16)

one bus cycle to confirm the command

two or three bus cycles to give the End Block Address (refer to Table 8, Table 9 and

Figure 16).

The Start Block Address must be nearer the logical LSB (Least Significant Bit) than End

Block Address.

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