PIMXRT406LCVJ4A datasheet(67/100 Pages) NXP

67 / 100 page

Electrical characteristics

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

4.8.3.4

HS200 mode timing

Figure 42 depicts the timing of HS200 mode, and Table 59 lists the HS200 timing characteristics.

Figure 42. HS200 mode timing

4.8.3.5

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50

mode is 1.8 V. The DC parameters for the NVCC_SD1 supply are identical to those shown in Table 22,

"Single voltage GPIO DC parameters," on page 30.

4.8.4

Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

Table 59. HS200 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

0.46 x tCLK

0.54 x tCLK

SD3

Clock High Time

tCH

0.46 x tCLK

0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

–1.6

0.74

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

1HS200 is for 8 bits while SDR104 is for 4 bits.

SD8

Card Output Data Window

tODW

0.5 x tCLK

—ns

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD4/SD5

SD2

SD3

SD1

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