ACE25QC160GLDPTH datasheet(33/73 Pages) ACE

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in standard SPI mode

The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a

“Set Burst with Wrap” (77H) instruction prior to E7H. The “Set Burst with Wrap” (77H) instruction can either

enable or disable the “Wrap Around” feature for the following E7H instructions. When “Wrap Around” is

enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte

page. The output data starts at the initial address specified in the instruction, once it reaches the ending

boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary

automatically until /CS is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then

fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read

instructions.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable

or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around

section within a page.

Figure16. Quad I/O word Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0),

SPI mode only)

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