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MAX14737 Scheda tecnica(PDF) 2 Page - Maxim Integrated Products |
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MAX14737 Scheda tecnica(HTML) 2 Page - Maxim Integrated Products |
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2 / 12 page ![]() (All voltages referenced to GND.) IN (Note 1), OUT, EN, EN .......................................-0.3V to +6V POK............................................. -0.3V to max (IN,OUT) + 0.3V Maximum Current into IN (DC) (Note 2) ..............................4.5A Peak Current into IN (10ms) ...................................................8A Continuous Power Dissipation (TA = +70°C) WLP (derate 11.9mW/°C above +70°C)......................952mW Operating Temperature Range........................... -40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range............................ -65°C to +150°C Soldering Temperature (reflow).......................................+260°C WLP Junction-to-Ambient Thermal Resistance (θJA) .....83.98°C/W (Note 3) (VIN = +2.1V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VIN = 4.3V, TA = +25°C, unless otherwise noted.) (Note 4) Electrical Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IN, OUT Input Voltage Range VIN 2.1 5.5 V Supply Current IIN VIN = 4.3V, no load 13 30 µA IN Shutdown Current IIN_Q Device disabled, VIN = 4.3V, VOUT = 0V 2 6 µA OUT Shutdown Current Device disabled, VOUT = 5V, VIN = 0V 2 6 µA OVP On-Resistance (IN to OUT) RON VIN = 4.3V, IOUT = 100mA, 15 22 mΩ Overvoltage Trip-Level Threshold VOVLO VIN rising MAX14736 4.600 4.700 4.800 V MAX14737 5.095 5.200 5.305 V Overvoltage Trip-Level Hysteresis VOVLO_ 100 mV Undervoltage Trip-Level Threshold VUVLO 2.015 V Undervoltage Trip-Level Hysteresis VUVLO_ 80 mV OUT Load Capacitance COUT 100 µF DIGITAL OUTPUT (POK) Output Voltage Low VOL ISINK = 100µA 0.4 V Output Voltage High VOH ISOURCE = 100µA 1.4 V MAX14736/MAX14737 Precision, Ultra-Fast, Low Supply Current, Bidirectional Overvoltage Protector www.maximintegrated.com Maxim Integrated │ 2 Note 1: Survives burst pulse up to ±40V with 2Ω minimum source resistance. Note 2: Limited by thermal design. Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics |
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