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PD69210 Scheda tecnica(PDF) 10 Page - Microchip Technology |
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PD69210 Scheda tecnica(HTML) 10 Page - Microchip Technology |
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10 / 21 page ![]() ...........continued PD69210 Pin PD69220 Pin Designation Type Description 24 24 xI2C_MESSAGE_READY OUT I2C message ready for reading by the host. Controller asserts this line low when it has an answer to the host. Therefore, the host can poll this line and initiate I2C read cycle only when the message is ready. After the host reads the data from the controller, this pin is asserted to high. (Active Low) 25 25 xINT_OUT OUT Interrupt output indication. This line is asserted low when a pre-configured event is in progress. (Active Low) 26 19 xRESET IN/OUT Host Reset input (Active Low). Controller can generate self-reset. In this case, the xRESET pin is driven low by the controller for 100 µs. See AN3361 for pin connection requirements. 27 27 xLED_LATCH2 OUT Latch signal for LED stream. (Active Low) 28 16 VSSD GND Ground. 29 - VDD_CORE Power 1.2 V core voltage connect 1 μF capacitor to VSSD. 30 15 VDD Supply Main 3.3 V supply. 31 10 SWD_CLK PD69210 use a 1 kΩ pull-up to 3.3 V. PD69220 leave open or use 1k pull-up. 32 13 SWD_DIO Leave open. ePAD ePAD ePAD Connect to VSSA. Must have sufficient copper mass to ensure adequate thermal performance. PD69210/PD69220 Pins © 2020 Microchip Technology Inc. Datasheet DS00003424A-page 10 |
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