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24CS512TE/MS Scheda tecnica(PDF) 19 Page - Microchip Technology |
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24CS512TE/MS Scheda tecnica(HTML) 19 Page - Microchip Technology |
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19 / 66 page ![]() 2018-2021 Microchip Technology Inc. DS20005769C-page 19 24CS512 6.6.2 ENHANCED SOFTWARE WRITE PROTECTION MODE When the EWPM bit is set to logic ‘1’, the 24CS512 is configured for a versatile software write protection scheme by segmenting the EEPROM array into eight independent 64-Kbit zones (see Table 6-2). Each of the eight zones can be write-protected by programming the corresponding bit in the Configuration register. The protection behavior can be made permanent by locking the Configuration register (see Section 9.5 “Locking the Configuration Register” for additional details). Note: Enhanced software write protection does not affect write operations to the Security and Configuration registers. TABLE 6-2: 24CS512 ZONE PROTECTION CONTROL Configuration Register Bit Protected Zone Protected Address Range SWP7 7 E000h-FFFFh SWP6 6 C000h-DFFFh SWP5 5 A000h-BFFFh SWP4 4 8000H-9FFFh SWP3 3 6000h-7FFFh SWP2 2 4000h-5FFFh SWP1 1 2000h-3FFFh SWP0 0 0000h-1FFFh |
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