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24CS512TE/P Scheda tecnica(PDF) 37 Page - Microchip Technology |
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24CS512TE/P Scheda tecnica(HTML) 37 Page - Microchip Technology |
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37 / 66 page ![]() 2018-2021 Microchip Technology Inc. DS20005769C-page 37 24CS512 12.0 DEVICE DEFAULT CONDITION The 24CS512 is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations of the EEPROM memory array. The Security register contains a preprogrammed, 128-bit serial number in the lower 16 bytes. The user-programmable portion (lockable ID page) is unlocked and is set to logic ‘1’, resulting in 128 bytes of FFh data. The Configuration register is set for Legacy Hardware Write Protection mode (EWPM = ‘0’) and is unlocked. |
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