8.

Write Protection

8.1

Hardware Write Protection

The AT24CSW01X/AT24CSW02X utilizes a hardware data protection scheme that allows the user to write‑protect the

GND or left floating.

Table 8-1. AT24CSW01X/AT24CSW02X Write-Protect Behavior

WP Pin Voltage

Part of the Array Protected

Full Array

GND

None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the

start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not

alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup

WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the Stop

condition that the WP pin must remain stable.

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the

device address, word address and data bytes. However, no write cycle will occur when the Stop condition is issued.

The device will immediately be ready to accept a new read or write command.

Figure 8-1. Write-Protect Setup and Hold Timing

8.2

Software Write Protection of the EEPROM Array

The AT24CSW01X/AT24CSW02X utilizes a software scheme that allows a portion or the entire EEPROM to be

inhibited from being written to by modifying the contents of the Write Protection register (WPR). If desired, the WPR

can be set so that it may no longer be modified, thereby making the current protection scheme permanent.

The status of the WPR can be determined by following a random read operation. Changing the state of the WPR is

accomplished with a byte write operation with the requirements outlined in this section.

Accessing the WPR requires the use of 1011b (Bh) as the device type identifier in the device address byte (see

Device Address Byte Requirements for Accessing the Write Protection Register). Following the device type identifier

are the hardware address bits (A2, A1, A0) for which the values are determined by the ordering code of the device

(see Table 6-2). Finally, bit 0 is the Read/Write Select bit where ‘1’ is used for reading and ‘0’ is used for writing.

AT24CSW01X/AT24CSW02X

Write Protection

and its subsidiaries

Datasheet

DS20006396B-page 21