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PLL650-04DCLR Scheda tecnica(PDF) 4 Page - PhaseLink Corporation

Il numero della parte PLL650-04DCLR
Spiegazioni elettronici  Low EMI Clock for 10/100 PHY and Gigabit Ethernet
PDF  6 Pages
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Produttore elettronici  PLL [PhaseLink Corporation]
Homepage  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PLL650-04DCLR Scheda tecnica(HTML) 4 Page - PhaseLink Corporation

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Preliminary
PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/31/05 Page 4
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
4.6
V
Input Voltage, dc
VI
-0.5
VDD+0.5
V
Output Voltage, dc
VO
-0.5
VDD+0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
-40
85
°C
Junction Temperature
TJ
125
°C
Lead Temperature (soldering, 10s)
260
°C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Frequency
10
24
27
MHz
Output Rise Time
0.8V to 2.0V with no load
1.5
ns
Output Fall Time
2.0V to 0.8V with no load
1.5
ns
Duty Cycle
At VDD/2
45
50
60
%
Max. Absolute Jitter
Short term
±150
ps
Max. Jitter, cycle to cycle
80
ps
Output to output skew
Measured at VDD /2 on the
CLKOUT pin
0
250
ps
PLL Lock Time
After VDD >90% VDD -END
Value
3
5
ms



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