PLL601-12

Dual Output PLL Clock with Selectable Odd Multiplier

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Selectable multipliers (x2.5, x2.75, x3, x4.25, x5,

x5.5, x5.75, x6, x6.25, x10, x11, x11.5, x12,

x12.5).

• Crystal input range, 13MHz to 31MHz (see Se-

lection Table for detailed acceptable input

ranges).

• Maximum output frequency: 312.5MHz

• 2 CMOS outputs.

• Selectable output drive (Standard or High-Drive).

• Selectable REF_CLK output.

• 3.3V operation.

• Available in 14-Pin SOIC.

DESCRIPTION

The PLL601-12 is a highly flexible XO with select-

able multipliers and two CMOS outputs (one of which

can be selected to be REF_CLK). Thanks to Phase-

Link’s advanced Phase Locked Loop technology, it

allows a wide choice of selectable multipliers that

permits the user to achieve useful frequencies from

standard low cost crystals. It accepts fundamental

parallel resonant mode crystals from 13 to 31MHz,

and is ideal to generate 156.25MHz from a standard

25MHz crystal.

BLOCK DIAGRAM

PIN CONFIGURATION

(Top View)

^: Internal pull-up.

1

2

3

4

5

6

7

VDD

8

9

10

11

12

13

14

XIN

XOUT

S3^

S2^

DRIVE_SEL^

GND

S0^

S1^

REF_SEL^

CLK2/

REF_CLK

VDD

CLK1

GND

XIN

XOUT

REF_SEL

CLK1

CLK2/REF_CLK

[S3,S0]

Oscillator

Amplifier

PLL

(Phase

Locked

Loop)