ECE1200 datasheet(8/87 Pages) MICROCHIP

8 / 87 page

ECE1200

DS00003093C Draft-page 8

 2018-2021 Microchip Technology Inc.

1.1.4

SYSTEM BLOCK DIAGRAM, ECE1200 AS SECONDARY ESPI SLAVE

Note 1: This configuration has two eSPI Slaves. The ECE1200 is the Secondary Slave device, with some limitations

imposed by the Host PCH. It can receive any of the fixed Legacy decodes, but may have only one Generic

I/O decode range and one Generic Memory decode range available to it from the PCH.

2: Each eSPI Slave has an individual eSPI_CS# input, and will be configured by the PCH hardware (as

directed by its Soft-Straps) to present its ALERT# events on its individual eSPI_ALERT# output pin.

3: The Primary eSPI Slave device will have the EC functionality, and will provide the mandatory eSPI hand-

shaking. The pin BOOT_DONE, strapped permanently low, inhibits these actions by the ECE1200.

ECE1200

SIO or I/O

Expander

PCH

PME#

LPC_EN

RSMRST#

SLP_S3#

SLP_S4#

SLP_S5#

SCI#

SMI#

SLP_LAN#

SLP_WLAN#

Expansion Module

Baseboard

LPC

ESPI Bus

LPC

Debug

Header

eSPI

Embedded

Controller

Type‐C Port

Controller

I2C

RESETI#

Flash

SPI

BOOT_DONE

PLTRST#

SUS_STAT#

RSMRST#

SUSCLK

eSPI_CS1#

eSPI_CS0# (Primary Slave)

(Secondary Slave)

Virtual or

Physical

PCH

To/From

Primary

Slave

eSPI_CS#

LPCPD#

SUSWARN#

eSPI_ALERT1#

ESPI

Bus

eSPI_ALERT0#

eSPI_ALERT#

LRESET#

(opt. to GPIO)

HOST_RST_ACK

(n/c typ)

SUSACK#

(recommended)

ESPI Bus

SUSWARN#

SUSACK#

Note 1

Note 2

Note 3

Note 4

Note 5

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