AT25SF641 datasheet(22/76 Pages) DIALOG

Il numero della parte	AT25SF641

Spiegazioni elettronici	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	76 Pages

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AT25SF641

DS-25SF641–111E–3/2018

cycle is finished and ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in Status Register will be cleared to 0.

Figure 7-6.

Write Status Register Instruction (SPI Mode)

Figure 7-7.

Write Status Register Instruction (QPI Mode)

7.7

Write Status Register-2 (31h)

The Write Status Register-2 instruction is to write only non-volatile Status Register-2 bits (CMP, QE and SRP1).

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

instruction code, and then writing the status register data byte as illustrated in Figure 7-8 and Figure 7-9.

Using Write Status Register-2 (31h) instruction, software can individually access each one-byte status registers via different

instructions.

AT25SF641 Scheda tecnica(PDF) 22 Page - Dialog Semiconductor