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PLL650-09SC Scheda tecnica(PDF) 2 Page - PhaseLink Corporation |
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PLL650-09SC Scheda tecnica(HTML) 2 Page - PhaseLink Corporation |
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2 / 5 page ![]() PLL650-09 Low Cost Network LAN Clock PIN DESCRIPTIONS Name Number Type Description XIN 1 I 25MHz fundamental crystal input (20pF CL parallel resonant). CL have been integrated into the chip. No external CL capacitor is required. XOUT 2 O Crystal output connection pin. 50MHz 5,7,8,9 O 50MHz outputs. N/C 14 - No connection. VDD 4,10,15,16 P 3.3V power supply. GND 3,6,11,12,13 P Ground. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/19/02 Page 2 |
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