Preliminary

PLL502-21

384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 08/10/01 Page 1

FEATURES

• Low phase noise output for the 384MHz to

768MHz range (-130 dBc at 10kHz offset).

• PECL output.

• 12 to 24MHz crystal input.

• Integrated crystal load capacitor: no external

load capacitor required.

• Output Enable selector.

• Wide pull range (+/-180 ppm)

• 3.3V operation.

• Available in 16 Pin TSSOP or SOIC.

DESCRIPTION

The PLL502-21 is a monolithic low jitter and low

phase noise (-130dBc/Hz @ 10kHz offset) VCXO IC

with PECL output, for 384MHz to 768MHz output

range. It allows the control of the output frequency

with an input voltage (VIN), using a low cost crystal.

The chip provides a pullable output at a frequency of

range of applications, including 622.08MHz for

SONET.

PIN CONFIGURATION

OE (Pin 5)

Output State

0 (Default)

Output enabled

1

Tri-state

Pin 5: Logical states are defined at PECL levels.

BLOCK DIAGRAM

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

VCO

Divider

XTAL

OSC

CLKBAR

OE

XIN

XOUT

CLK

VIN

VARICAP

1

2

3

4

5

6

7

8

VDD

9

10

11

12

13

14

15

16

VDD

XIN

XOUT

OE

VIN

GND

GND

VDD

GND_BUF

CLKBAR

VDD_BUF

CLK

GND_BUF

GND

GND