®

TQL9066

50 – 1500 MHz Dual LNA

Data Sheet March 1, 2018 | Subject to change without notice

8 of 10

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Pin Configuration and Description

7

8

6

5

14

13

15

16

12

11

10

9

1

2

3

4

GND

GND

RFin2/

Vg2

RFin1/

Vg1

GND

GND

RFout2/

Vd2

RFout1/

Vd1

DC

Bias 1 Vpd1 Ictrl1

NA

DC

Bias 2

Vpd2 Ictrl2

NA

Backside Paddle - RF/DC GND

Pin 1 Reference Mark

Pin No.

Label

Description

1

RFin1/Vg1 RF input pin for channel 1. Gate voltage bias pin for channel 1.

2, 3

GND

No internal connection but should be grounded to provide PCB mounting integrity and

isolation between the two RF paths.

4

RFin2/Vg2 RF input pin for channel 2. Gate voltage bias pin for channel 2.

5

DC Bias 2

DC out bias for channel 2

6

Vpd2

Power down control voltage for channel 1

7

Ictrl2

Channel 2 drain current control

8, 13

NA

No internal connection. These pins can be left floating or grounded.

10, 11

GND

Internally connected. These pins must be externally grounded for functionality.

9

RFout2/Vd2 RF output pin for channel 2. Gate voltage bias pin for channel 2.

12

RFout1/Vd1 RF output pin for channel 1. Drain voltage bias pin for channel 1.

14

Ictrl1

Channel 1 drain current control

15

Vpd1

Power down control voltage for channel 1

16

DC Bias 1

DC out bias for channel 1

Backside Paddle

RF/DC GND

RF/DC Ground. Follow recommended via pattern and ensure good solder attach for

best thermal and electrical performance.

Evaluation Board PCB Information

TriQuint PCB 1094098 Material and Stack-up

1 oz. Cu bottom layer

Rogers 4003

ε

1 oz. Cu top layer

0.020 ± 0.002

Finished Board

Thickness

50 o

hm line dimensions: width = .040”, spacing = .020”