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3AI75 Scheda tecnica(PDF) 7 Page - Integrated Circuit Systems

Il numero della parte 3AI75
Spiegazioni elettronici  75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
PDF  12 Pages
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Produttore elettronici  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com
Logo ICST - Integrated Circuit Systems

3AI75 Scheda tecnica(HTML) 7 Page - Integrated Circuit Systems

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843AG-106
www.icst.com/products/hiperclocks.html
REV. A JANUARY 10, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
drive 50
Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 2A and 2B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
FREQUENCY STABILITY
The table shown provides a basic guideline in selecting
the proper quartz crystal that meets a timing budget of
±100ppm. For more information on selecting the proper
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and Accuracy for FemtoClock™ .



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