ICS601-25 datasheet(1/5 Pages) ICST

Il numero della parte	ICS601-25

Spiegazioni elettronici	LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

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Produttore elettronici	ICST [Integrated Circuit Systems]

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ICS601-25

MDS 601-25 C

1

Revision 071505

Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m

LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

Description

The ICS601-25 is a low-cost, low phase noise, high

performance clock synthesizer for applications which

require low phase noise, low jitter, and low skew fanout.

It is ICS’ lowest phase noise multiplier, and also the

lowest CMOS part in the industry. Using ICS’ patented

analong and digital Phase Locked Loop (PLL)

techniques, the chip accepts a 10-27 MHz crystal or

clock input, and produces output clocks up to 156 MHz.

Features

• Packaged in 20-pin SSOP

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 156 MHz

• Low phase noise: -132 dBc/Hz at 10 kHz

• Five low skew (<250 ps) outputs

• Low jitter - 18 ps one sigma at 125 MHz

• Full swing CMOS outputs with 25 mA drive capability

at TTL levels

• Powerdown mode lowers power consumption

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• Available in Pb (lead) free package

• Operating voltage of 3.3 V

Block Diagram

CLK1

ROM Based

Multipliers

VCO

Divide

X1/ICLK

X2

Crystal or

clock input

Crystal

Oscillator

Reference

Divider

Phase

Comparator

VDD

Charge

Pump

Loop

Filter

VCO

S3:0

PD

CLK5

CLK4

CLK3

CLK2

5

GND

3

4

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