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ICS8523I Scheda tecnica(PDF) 10 Page - Integrated Circuit Systems |
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ICS8523I Scheda tecnica(HTML) 10 Page - Integrated Circuit Systems |
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10 / 16 page ![]() 8523BGI www.icst.com/products/hiperclocks.html REV. C SEPTEMBER 16, 2004 10 Integrated Circuit Systems, Inc. ICS8523I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER SCHEMATIC EXAMPLE Figure 5 shows a schematic example of the ICS8523I. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near the 1.8V LVHSTL Driver Zo = 50 Zo = 50 C2 0.1u R5 50 R6 50 R10 50 1.8V R11 1K R3 50 Zo = 50 Ohm U3 8523 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK NC NC VDD nQ3 Q3 VDDO nQ2 Q2 nQ1 Q0 nQ0 VDDO Q1 Zo = 50 + - Zo = 50 Ohm Zo = 50 R4 50 R12 1K R1 50 1.8V 1.8V + - R7 50 R2 50 3.3V C3 0.1u R9 50 + - Zo = 50 R8 50 + - Zo = 50 3.3V Zo = 50 Zo = 50 C1 0.1u FIGURE 5. ICS8523I HSTL BUFFER SCHEMATIC EXAMPLE power pin. For ICS8523I, the unused clock outputs can be left floating. |
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