ICS85222-01 datasheet(6/13 Pages) ICST

6 / 13 page

85222AM-01

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 15, 2005

Integrated

Circuit

Systems, Inc.

ICS85222-01

DUAL LVCMOS / LVTTL-TO-

DIFFERENTIAL HSTL TRANSLATOR

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

DD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLKx

nCLKx

VDD

INPUTS:

CLK INPUT:

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the CLK input to

ground.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

HSTL OUTPUT

All unused LVHSTL outputs can be left floating. We

recommend that there is no trace attached. Both sides of the

differential output pair should either be left floating or

terminated.

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