2

ICSSSTV16857

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels

except for the RESET# input which is LVCMOS.

Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the

positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS

levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and

when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and

clock are switched off.

R

E

B

M

U

N

N

I

PE

M

A

N

N

I

PE

P

Y

TN

O

I

T

P

I

R

C

S

E

D

,

8

1

,

9

1

,

0

2

,

3

2

,

4

2

,

6

,

7

,

0

1

,

1

1

,

4

1

,

5

1

1

,

2

,

5

)

1

:

4

1

(

QT

U

P

T

U

Ot

u

p

t

u

o

a

t

a

D

,

2

2

,

3

1

,

8

,

3

6

4

,

6

3

,

7

2

D

N

GR

W

Pd

n

u

o

r

G

1

2

,

6

1

,

2

1

,

9

,

4Q

D

D

VR

W

Pe

g

a

t

l

o

v

y

l

p

p

u

s

t

u

p

t

u

O

,

1

3

,

0

3

,

9

2

,

6

2

,

5

2

,

2

4

,

1

4

,

0

4

,

3

3

,

2

3

8

4

,

7

4

,

4

4

,

3

4

)

1

:

4

1

(

DT

U

P

N

It

u

p

n

i

a

t

a

D

8

3K

L

CT

U

P

N

It

u

p

n

i

k

c

o

l

c

e

v

i

t

i

s

o

P

9

3#

K

L

CT

U

P

N

It

u

p

n

i

k

c

o

l

c

e

v

i

t

a

g

e

N

5

4

,

7

3

,

8

2D

D

VR

W

Pe

g

a

t

l

o

v

y

l

p

p

u

s

e

r

o

C

4

3#

T

E

S

E

RT

U

P

N

I)

w

o

l

e

v

i

t

c

a

(

t

e

s

e

R

5

3F

E

R

VT

U

P

N

Ie

g

a

t

l

o

v

e

c

n

e

r

e

f

e

r

t

u

p

n

I