ICS16857C datasheet(1/8 Pages) ICST

Il numero della parte	ICS16857C

Spiegazioni elettronici	DDR 14-Bit Registered Buffer

PDF	8 Pages

Scroll/Zoom	100%

Produttore elettronici	ICST [Integrated Circuit Systems]

Homepage	http://www.icst.com

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1 / 8 page

Integrated

Circuit

Systems, Inc.

ICSSSTV16857C

0002F—10/25/02

Pin Configuration

DDR 14-Bit Registered Buffer

Truth Table

1

Block Diagram

Notes:

1.

H = High Signal Level

L = Low Signal Level

↑ = Transition LOW-to-HIGH

↓ = Transition HIGH -to LOW

X = Irrelevant

2.

Output level before the indicated

steady state input conditions were

established.

s

t

u

p

n

Is

t

u

p

t

u

O

Q

#

T

E

S

E

RK

L

C#

K

L

CD

Q

L

r

o

X

g

n

i

t

a

o

l

F

r

o

X

g

n

i

t

a

o

l

F

r

o

X

g

n

i

t

a

o

l

F

L

H

↑↓

HH

H

↑↓

LL

HH

r

o

LH

r

o

LX

Q0 )

2

(

48-Pin TSSOP & TVSOP

6.10 mm. Body, 0.50 mm. pitch = TSSOP

4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)

Recommended Applications:

•

DDR Memory Modules

•

Provides complete DDR DIMM logic solution with

ICS93V857 or ICS95V857

•

SSTL_2 compatible data registers

Product Features:

•

Differential clock signal

•

Meets SSTL_2 signal data

•

Supports SSTL_2 class I & II specifications

•

Low-voltage operation

- VDD = 2.3V to 2.7V

•

48 pin TSSOP package

Q1

Q2

GND

VDDQ

Q3

Q4

Q5

GND

VDDQ

Q6

Q7

VDDQ

GND

Q8

Q9

VDDQ

GND

Q10

Q11

Q12

VDDQ

GND

Q13

Q14

D1

D2

GND

VDD

D3

D4

D5

D6

D7

CLK#

CLK

VDD

GND

VREF

RESET#

D8

D9

D10

D11

D12

VDD

GND

D13

D14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

CLK

CLK#

38

39

48

35

34

D1

VREF

RESET#

To 13 Other Channels

Q1

1

CLK

R

D1

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